Proposed Low-dropout Regulator Research Articles

Three-Stage CMOS LDO with Optimized Power and Dynamic Performance for Portable Devices

Low dropout (LDO) regulators are crucial components in power management systems for portable, i.e., battery-powered, devices. However, the design of LDO regulators presents a challenging trade-off between dynamic performance, power consumption, and area efficiency. This paper proposes a novel LDO regulator design that addresses these challenges by employing the reverse nested Miller compensation (RNMC) with current buffers embedded within the own class AB high gain error amplifier (EA) topology, and a time response enhancement circuit (TREC). High-gain (>120 dB) class AB EA renders good regulation performance with enhanced dynamic performance. The proposed compensation scheme improves the gain bandwidth product (GBW) and stability of the regulator, while the TREC reduces overshoot and undershoot during load transients without additional steady-state power consumption. Post-layout simulations confirm the robustness of the proposed 180 nm CMOS design across a wide range of operating conditions, achieving a regulated output voltage of 1.8 V with 100 mV dropout, good load and line regulating performance, and excellent load transient response with reduced undershoot and overshoot at minimum power (Iq = 13.8 μA) and area (314 μm × 150 μm) consumption. The proposed LDO regulator thus offers a compelling compromise between power consumption, area efficiency, and dynamic performance, making it highly suitable for portable applications.

Design of Destruction Protection and Sustainability Low-Dropout Regulator Using an Electrostatic Discharge Protection Circuit

In terms of sustainable power semiconductors, the embedding of an electrostatic discharge (ESD) protection circuit in an integrated circuit (IC) is an important aspect. In order for the semiconductor circuit to operate continuously or stably, a sufficient protection circuit against external surges must be configured. The purpose of this thesis is not only to effectively operate the low-dropout (LDO) regulator according to the load current, but to also secure high reliability against ESD situations by embedding an ESD protection circuit at the IC level. Moreover, the existence and nonexistence of an ESD protection circuit at the IC level is directly related to reliability. The proposed LDO regulator has high reliability against ESD situations using an embedded silicon controlled rectifier (SCR)-based ESD protection circuit in the I/O clamp and power clamp. The results revealed that the LDO regulator can not only effectively control the output voltage according to the load current, but it can also stably maintain the output voltage against the ESD surge. Moreover, the proposed LDO regulator with an embedded ESD protection circuit implemented in a 0.13 μm BCD process maintained an undershoot voltage of 21 mV and overshoot voltage of 19 mV for a load current of 300 mA.

A Nested Miller Compensation with a large feed-forward transconductor for capacitor-less flipped voltage follower low dropout regulator

In this paper, a capacitor-less flipped voltage follower (FVF) low dropout (LDO) regulator using nested miller compensation with a large feed-forward transconductor (NMCLFT) is presented. The LDO regulator is a dual-summing based three-stage high-gain structure and NMCLFT stabilizes the feedback loop for the load current ranges of 0 to 50 mA with load capacitances of 0 to 100 pF. This LDO regulator uses the multiple feed-forward paths which enhance the unity gain bandwidth (UGB) as well as the transient responses. The large feed-forward transconductor separates the non-dominant complex poles of nested miller compensation (NMC) into two simple poles and pushes one of the poles into high-frequency. It also provides a strong low-frequency left-half plane (LHP) zero and pushes right-half plane (RHP) zero of NMC into high-frequency and makes the multi-pole LDO regulator into a single-pole LDO for all the cases, from light load to heavy load with different load capacitor corners. The NMCLFT eliminates the minimum load current and minimum load capacitance constraints with improved transient response. The proposed LDO regulator achieves the settling time of 120 ns with the minimum edge time of 10 ns for the load current ranges of 0 to 50 mA and the load capacitance ranges of 0 to 100 pF. This LDO is implemented in 130 nm CMOS technology and it consumes a quiescent current of 63μA.

Design of capacitor-less LDO regulator with SCR-based ESD protection using dual push-pull stage

ABSTRACT The external capacitors of conventional LDO (Low Drop Out) regulator have a function to improve the transient response characteristics affected by the overshoot and undershoot. However, the LDO regulator proposed in this study is replaced the function of the external output capacitor with a dual push-pull stage and is achieved a fast transient response by a newly added control path to replace the function of the capacitor removed along with the existing feedback path. The proposed LDO regulator can also be provided the improved ESD (Electro Static Discharge) robustness characteristics by applying the SCR (Silicon Control Rectifier)-based ESD (Electro Static Discharge) protection device embedded into the output node and power line. The LDO regulator with dual push-pull circuit proposed in this study was operated at a maximum load current of 100 mA, an output voltage of 3 V, and an input voltage range of 3.3 ~ 4.5 V. As a result of the measurement, an undershoot voltage of 110 mV and an overshoot voltage of 123 mV were maintained when a load current of 100 mA was applied. Further, the ESD robustness characteristic of HBM is guaranteed at 8kV or higher.

Design of current detection LDO regulator with silicon controlled rectifier based electrostatic discharge protection circuit to provide optimized voltage and power for system‐on‐chip applications

Various levels of circuits and systems in the ultra-low nanometer fabrication process should be considered to implement a system-on-chip (SOC) application to reduce power consumption. This letter is intended to propose a current detection structure that supplies and discharges additional current along the load current to provide the optimized voltage and power for SOC applications. The proposed electrostatic discharge (ESD) protection circuit placed on the power line and I/O has improved the reliability by preventing the direct or indirect destruction of the internal integrated circuit (IC) due to ESD. In addition, the proposed low drop out (LDO) regulator for the low-voltage applications has combined an ESD protection circuit to secure the high reliability of the IC. The proposed LDO regulator is implemented with a 0.18-μm BCD process and is kept an undershoot voltage of 23 mV and an overshoot voltage of 25 mV for a load current of 200 mA.

A capacitor-free fast-response low-dropout voltage regulator

An off-chip capacitor-free low-dropout (LDO) regulator using an improved frequency compensation scheme is proposed. The proposed LDO regulator employs a class-AB error amplifier and a load-current tracker. Outstanding line regulation, load regulation and transient response are achieved. SPICE simulation based on SMIC 0.35 µm CMOS technology shows that the proposed LDO regulator has a low frequency gain over 100 dB and a unity-gain bandwidth in the MHz range. In terms of transient response, the 1% settling time is shorter than 0.2 µs.

A Hybrid-Mode LDO Regulator with Fast Transient Response Performance for IoT applications

A hybrid-mode low-drop out (LDO) voltage regulator with fast transient response performance for IoT applications is proposed in this paper. The proposed LDO regulator consist of two sections. First section is an analog regulator which includes a folded cascode operational amplifier to achieve good PSRR. Second section is current DAC and detectors whitch includes a cource current DAC, sink current DAC, undershoot detectors, and overshoot detectors. The current DAC and detectors are designed to obtain a low drop out and fast transient response. The proposed hybrid-mode LDO voltage regulator has been designed, simulated and layouted in Cadence using TSMC 90 nm CMOS technology. The input range of the LDO regulator is 1.2–2.0 V, and it can produces an output voltage of 1.2V. The LDO regulator achieves 58uA quiescent current, -69 PSRR @ 1 KHz noise frequency and an output voltage drop of around 60mV for a load current step of 100 mA. The final design occupies approximately 0.09 mm2.

A VERY LOW-DROPOUT VOLTAGE REGULATOR IN 0.18-M CMOS TECHNOLOGY FOR POWER MANAGEMENT SYSTEM

This paper proposes the design of a very low-dropout (LDO) voltage regulator in 0.18-mm CMOS technology. The proposed LDO regulator consists of voltage reference, symmetrical operational transconductance amplifier (OTA), PMOS transistor, resistive feedback network and output capacitor. The NMOS symmetrical OTA is implemented as an error amplifier and a PMOS transistor is employed as a pass device to improve gain and minimize low dropout voltage, respectively. The proposed design is simulated using Spectre simulator in Cadence software to verify its regulator performance. The simulation results show that the proposed LDO is capable to operate from a supply voltage of 1.7-2.0 V with a low dropout voltage of 19.3 mV at a maximum 50 mA load current to regulate output voltage 1.5 V. The active chip is 2.96 mm2 in size. The performance of the proposed LDO is suitable to enhance power management for system on chip (SoC) applications.  

A Low-Power High-Gain Low-Dropout Regulator for Implantable Biomedical Applications

This paper presents an ultra-low-power and high-gain low-dropout (LDO) regulator. It is based on the flipped voltage follower cell with an adaptive biasing technique that is suitable for implantable biomedical applications. The error amplifier for the proposed regulator consists of two cross-coupled common-gate cells and a pseudo-folded-cascode structure to increase the regulator’s loop gain. In addition, three different compensation techniques including Miller, cascode, and Q-reduction are simultaneously utilized at the LDO regulator to achieve high stability despite having the minimum load current and ultra-low power consumption. The proposed LDO regulator has been simulated in TSMC 90-nm CMOS technology with minimum power consumption of 2.8 µW at no load. Post-layout simulation results show that the proposed LDO regulator is stable over load currents from 30 µA to 40 mA with a maximum on-chip CL of 100 pF. Moreover, the voltage regulator settles in less than 850 ns at 0.75 V output voltage that is achieved in response to a load transient step of 40 mA with a rise time of 200 ns. Besides, the obtained line and load regulations are significantly improved to 1 mV/V and 36 µV/mA, respectively.

A High-Performance LDO Regulator Enabling Low-Power SoC With Voltage Scaling Approaches

Low-power system-on-a-chip (SoC) with multiple voltage domains often adopts voltage scaling approaches to optimize power usage while maintaining enough performance. Voltage regulators having flexible output configurability, fast transient response, and high-power noise rejection ability are indispensable for this application scenario. A low-dropout (LDO) regulator was proposed in this article to convert an input of 1.9–1.1 V to an output of 1.1–0.2 V with a 10-mV tuning resolution by raising the concept of programmable recursively divide-by-two resistor array (PRDTRA). A high gain-bandwidth main regulation loop of the proposed LDO regulator was accompanied by a transient acceleration (TA) path and a unity power noise gain generator to achieve a 28-mV output variation during 0–100-mA load transient test while keeping a 60-dB power supply rejection ratio (PSRR) over a frequency band of 0–1 MHz. Performance evaluations show the performance superiority of the proposed LDO regulator.

A Fully On-Chip Low-Dropout Regulator for SoC applications

Abstract This paper presents the design of a capacitor-less low-dropout (LDO) regulator for SoC applications such as mobile phones. To eliminate the external capacitor, a novel compensation circuit is designed which consists of a sense amplifier, a current amplifier, and a PMOS switch. The proposed LDO regulator provides a load current of 50 mA with a drop-out voltage of 240 mV while consuming 10 µA of quiescent current. The novel compensation circuit provides a high-speed path during load transients which reduces the settling time of the LDO. Undershoots /overshoots in the output during load transients are 142.5 mV/245.7 mV with settling time of only 96 ns and load regulation of 7.8 µV/mA. Moreover, this LDO provides a regulated output of 1.2 V for an input voltage ranging from 1.44 V to 3 V. Additionally, an op-amp based band-gap reference (BGR) circuit having a temperature coefficient of 20.49 ppm/˚C is designed to supply a reference voltage (VREF) of 1.2 V to the LDO. The proposed system is designed in UMC 90 nm technology. Monte Carlo simulations show the immunity of design to process and mismatch variations.

Fast transient low‐dropout regulator with undershoot and settling time reduction technique

This article proposes an external capacitor-less low-dropout (LDO) regulator with undershoot and settling time reduction technique for fast transient response. In the proposed LDO, a feedback capacitor is applied instead of a complicated voltage-spike detection circuit to reduce undershoot voltage and settling time without consuming additional quiescent current. When an undershoot or overshoot voltage occurs in the load transient response, the undershoot voltage and settling time are reduced by increasing the gate discharging current or gate charging current of the pass transistor by the current flowing through the feedback capacitor. An adaptively biased single-stage error amplifier with a cross-coupled pair is used to improve stability without external capacitors at low quiescent current consumption. The proposed LDO regulator is implemented with a 0.18 μm CMOS process and consumes a quiescent current of 3.0 μA at a minimum load current of 0.1 mA. Compared with the conventional LDO regulator, the proposed LDO regulator reduces the undershoot voltage by 53.3% and the settling time by 55.5% without consuming additional quiescent current.

A Quiescent 407-nA Output-Capacitorless Low-Dropout Regulator With 0–100-mA Load Current Range

An ultralow quiescent current output-capacitorless low-dropout (LDO) regulator dedicated to Internet-of-Things applications is presented. This is based on an improved adaptive-stage adaptively biased architecture together with the novel frequency compensation to achieve the good stability and fast transient response under ultralow bias current. Validated by the CMOS 0.18- $\mu \text{m}$ technology, the chip area is 0.055 mm2. The proposed LDO regulator consumes only 407-nA quiescent current at no-load current while providing a 1-V output with a maximum load current of 100 mA from a 1.2-V power supply. The adaptive frequency compensation is presented, including a new transistor degeneration frequency compensation (TDFC) to sustain the stability at ultralow quiescent bias. Besides, it also includes Q-reduction and Miller-RC compensation schemes to ensure the stability for full load current range. In addition, a substantial improved transient response is obtained by the proposed distributed overshoot reduction circuit together with the TDFC scheme and the adaptively feed-forward biasing topology. The measured results have shown that the undershoot/overshoot voltage is 117 mV/35.33 mV and the output can settle in $1.56~\mu \text{s}$ with 1% accuracy. Compared to fixed-biased and adaptively biased architectures, it shows the lowest value in figure of merit (FOM) at the quiescent state. Compared to adaptively biased architectures, it shows the improved FOM at the maximum quiescent state.

A 2 × VDD-Enabled Output-Capacitor-Free Low-Dropout Regulator with Fast Transient Response for Low-Cost System-on-Chip

This paper presents a [Formula: see text]-enabled output-capacitor-free CMOS low-dropout (LDO) regulator with fast transient response for cost-effective system-on-chip (SoC) power management applications with elevated-[Formula: see text] supply. All the MOS transistors used in the proposed LDO regulator are low voltage (LV) MOSFETs, hence saving the high voltage devices fabrication cost required in a conventional design. Two LV power transistors are cascaded in the power train. A mid-rail regulator is used to generate [Formula: see text] voltage for the power transistors as well as the main error amplifier to guarantee safe operation. The mid-rail regulator employs stacking transistors to handle the high supply voltage. Moreover, Miller compensation with adaptive biasing is used to achieve good stability and fast transient response. A proof-of-concept design is fabricated in a standard 0.18-[Formula: see text]m CMOS process which achieves 3.3–3.6[Formula: see text]V nominal input, 3.1[Formula: see text]V nominal output and 100[Formula: see text]mA loading capability with all the transistors being 1.8[Formula: see text]V MOSFETs.

An ultra-low power output capacitor-less low-dropout regulator with slew-rate-enhanced circuit * * Project supported by the National Natural Science Foundation of China (Nos. 61401137, 61404043, 61674049).

An ultra-low power output-capacitorless low-dropout (LDO) regulator with a slew-rate-enhanced (SRE) circuit is introduced. The increased slew rate is achieved by sensing the transient output voltage of the LDO and then charging (or discharging) the gate capacitor quickly. In addition, a buffer with ultra-low output impedance is presented to improve line and load regulations. This design is fabricated by SMIC 0.18 μm CMOS technology. Experimental results show that, the proposed LDO regulator only consumes an ultra-low quiescent current of 1.2 μA. The output current range is from 10 μA to 200 mA and the corresponding variation of output voltage is less than 40 mV. Moreover, the measured line regulation and load regulation are 15.38 mV/V and 0.4 mV/mA respectively.

Capless LDO Regulator Achieving −76 dB PSR and 96.3 fs FOM

The performance of switching devices such as display driver ICs is degraded by large power supply noise at switching frequencies from a few hundreds of kilohertz to a few megahertz. In order to minimize the power supply noise, a low-dropout (LDO) regulator with higher power supply rejection (PSR) is essential. In this brief, a capless LDO regulator with a negative capacitance circuit and voltage damper is proposed for enhancing PSR and figure of merit (FOM), respectively, in switching devices. The proposed LDO regulator is fabricated in a $0.18~\boldsymbol {\mu }\text{m}$ CMOS. Measurement results show that the proposed LDO regulator achieves −76 dB PSR at 1 MHz and 96.3 fs FOM with a total on-chip capacitance of as small as 12.7 pF.

Fully integrated, low drop-out linear voltage regulator in 180 nm CMOS

This paper presents a capacitor-free low dropout (LDO) linear regulator based on a dual loop topology. The regulator utilizes two feedback loops to satisfy the challenges of hearing aid devices, which include fast transient performance and small voltage spikes under rapid load-current changes. The proposed design works without the need of a decoupling capacitor connected at the output and operates with a 0---100 pF capacitive load. The design has been taped out in a $$0.18\,\upmu \hbox {m}$$0.18μm CMOS process. The proposed regulator has a low component count, area of $$0.012\, \hbox {mm}^2$$0.012mm2 and is suitable for system-on-chip integration. It regulates the output voltage at 0.9 V from a 1.0---1.4 V supply. The measured results for a current step load from 250 to 500 $$\upmu \hbox {A}$$μA with a rise and fall time of $$1.5\,\upmu \hbox {s}$$1.5μs are an overshoot of 26 mV and undershoot of 26 mV with a settling time of $$3.5\,\upmu \hbox {s}$$3.5μs when $${C_L}$$CL between 0 and 100 pF. The proposed LDO regulator consumes a quiescent current of only $$10.5\,\upmu \hbox {A}$$10.5μA. The design is suitable for application with a current step edge time of 1 ns while maintaining $$\Delta V_{out}$$ΔVout of 64 mV.

Ultralow-quiescent-current and wide-load-range low-dropout linear regulator with self-biasing technique for micropower battery management

In this paper, we present a 151 nA quiescent and 6.8 mA maximum-output-current low-dropout (LDO) linear regulator for micropower battery management. The LDO regulator employs self-biasing and multiple-stacked cascode techniques to achieve efficient, accurate, and high-voltage-input-tolerant operation. Measurement results demonstrated that the proposed LDO regulator operates with an ultralow quiescent current of 151 nA. The maximum output currents with a 4.16 V output were 1.0 and 6.8 mA when the input voltages were 4.25 and 5.0 V, respectively.

Improved Transient Response Capacitor-less Low Drop-out (LDO) Regulator using Current Mode Transconductance Amplifier and Slew Rate Enhancement Technique

paper presents a capacitor-less low drop-out (LDO) regulator with current mode transconductance amplifier & slew-rate enhancement circuit. The proposed current mode transconductance amplifier as error amplifier improves the slew rate & slew- rate enhancement circuit further senses the transient voltage at the output of the LDO to increase the bias current of the error amplifier for a short duration. Hence, transient response of LDO has been further improved using these techniques. The proposed LDO regulator will be designed and simulated in 180nm CMOS technology.

응답 시간을 향상 시킨 외부 커패시터가 없는 Low-Dropout 레귤레이터 회로

In this paper, an output-capacitorless, low-dropout (LDO) regulator is designed, which consumes quiescent current. Proposed LDO regulator is realized using two amplifier for good load regulation and fast response time, which provide high gain, high bandwidth, and high slew rate. In addition, a one-shot current boosting circuit is added for current control to charge and discharge the parasitic capacitance at the pass transistor gate. As a result, response time is improved during load-current transition. The designed circuit is implemented through a CMOS process. We experimentally verify output voltage fluctuation of 260mV and recovery time of at maximum load current 200mA.